In general, image sensors are semiconductor devices for converting optical images into electric signals, and are generally classified as charge coupled device (CCD) image sensors or complementary metal oxide semiconductor (CMOS) image sensors.
CCDs require high power consumption and many complicated manufacturing processes and are difficult to be made in a single chip.
For this reason, the CMOS image sensor has recently been spotlighted.
The CMOS sensor includes a photodiode (PD) and a metal oxide semiconductor (MOS) transistor in each unit pixel and sequentially detects the electric signals of each unit pixel through the MOS transistor in a switching mode to realize images.
Since the CMOS image sensor employs a CMOS manufacturing technology, it requires low power consumption and only about twenty masks in a manufacturing process. Accordingly, the manufacturing process of the CMOS image sensor is typically more desirable.
In addition, since the CMOS image sensor can be realized in a single chip together with various signal processing circuits, it has attracted considerable attention as a next generation image sensor.
The conventional CMOS image sensor will now be described with reference to the accompanying drawings.
FIG. 1 is an equivalent circuit diagram illustrating a 4T-type CMOS image sensor including one photodiode and four transistors. FIG. 2 is layout view showing a unit pixel of a conventional 4T-type CMOS image sensor.
As illustrated in FIGS. 1 and 2, the unit pixel of the 4T-type CMOS image sensor includes a photodiode PD (10) serving as a photoelectric conversion portion and four transistors Tx, Rx, Dx, and Sx.
The four transistors are transfer, reset, drive and selection transistors Tx (20), Rx (30), Dx (40) and Sx (50), respectively. Also, a load transistor is connected electrically to a drain terminal of the selection transistor, which is an output terminal of each unit pixel.
FIG. 3 is a sectional view illustrating the conventional 4T type CMOS image sensor.
As seen in FIG. 3, the conventional 4T-type CMOS image sensor includes a P− type semiconductor substrate 1 on which an active region and an isolation region are defined, an isolation layer 5 formed in the isolation region, and a well region formed on the surface of the semiconductor substrate 1. The conventional 4T-type CMOS image sensor also has gate insulating layers (not shown), gate electrodes 20 and 30, and spacers 125 formed at both sides the gate insulating layers and the gate electrodes. In addition, an N− type lightly doped drain region (not shown) is formed on the surface of the semiconductor substrate 1 below the spacers 125.
An N+ type well region is formed on the surface of the semiconductor substrate 1 at both sides of the gate electrodes 20, 30, 40, 50, and serves as a source/drain region of each transistor. A floating diffusion node region 60 is the N+ type well region formed between the transfer transistor Tx and the reset transistor Rx.
However, the conventional CMOS image sensor has the following problems.
According to the method of manufacturing the conventional CMOS image sensor, the floating diffusion node region is generally open in a mask for forming a junction region of a logic section after forming a photodiode. As a reference, the junction region of the logic section refers to a floating diffusion region, which is described herein.
For this reason, in the method of manufacturing the conventional CMOS image sensor, during ion implantation for forming the junction region of the logic section, the ions are implanted into the floating diffusion node region. This makes it difficult to independently adjust a capacitance value of the floating diffusion (FD) region.
In addition, since one mask is conventionally used, a process for reducing junction leakage of the floating diffusion node region is needed.